This application claims priority to Japanese Patent Application No. P2000-268393.
1. Field of the Invention
The present invention relates to a method for generating a behavior model description of a circuit and an apparatus for logic verification, and more particularly relates to a method for generating a behavior model description of a circuit for system level design and verification, and an apparatus for logic verification of a complete system or a part of a logic circuit system.
2. Description of the Background
Heretofore, where logic circuit systems such as a digital synchronous computer and a system LSI are incorporated in a LSI, a design method has been known in which a software programming language such as C and/or C++ language is applied in system level design. The system function is described using these programming languages, is compiled on a computer, and is then executed after linking with a software library. As a result, the functional verification of a logic circuit system by way of the functional simulation may be realized.
However, this design method focuses only on the system function of the logic circuit system, and the method is not capable of describing or verifying the system behavior including the input/output timing of various signals that are to be considered when the logic circuit system is wholly or partially implemented in hardware.
On the other hand, a system design method that realizes the desired function of the entire system by combining the software to be executed on a processor, an existing hardware circuit module, and newly designed hardware (to be verified) to supplement the deficiency of the function has been known. In the following description, a central processing unit is regarded as one of the hardware modules.
In the case of a logic circuit system having a plurality of circuit modules, it is preferably designed so that the interface of each circuit module is acceptable for a signal transmission procedure (referred to as a xe2x80x9cprotocolxe2x80x9d) between the various modules.
A technique for describing the interface of the circuit modules so that the input/output timing of various signals may be found is described in, for example, K. Suzuki et al. xe2x80x9cOwL: An Interface Description Language for IP Reusexe2x80x9d IEEE CICC, ""99, pp. 403-406. A similar technique is disclosed in Japanese Published Unexamined Patent Application No. Hei 12-123064 (Japanese Patent Application No. Hei 10-297827).
In the interface description methodology, a combination of signal values of the input/output signal in the circuit module is represented by an alphabet name, and each interface of the circuit module is defined as a set of alphabet name sequences. Furthermore, the regular expression is used as the method for expressing the sequences and the method for expressing the set to thereby realize various interface expressions with a relatively small amount of description. The interface description methodology disclosed in the Japanese Published Unexamined Patent Application No. Hei 12-123064 is referred to hereinafter as the xe2x80x9cOwL interface description methodology.xe2x80x9d
Heretofore, logic simulation has been used widely to verify the hardware design of a logic circuit system. In logic simulation, the design is described by way of a hardware description language, and the design is executed using a simulator (it is simulated). Where the logic circuit system has a plurality of circuit modules, a new circuit module (newly designed part) to be verified is entered as a detailed description that indicates the design result to the simulator, and an old or known circuit module (a peripheral logic module) that is to be connected to the module under verification is entered as a simplified description to the simulator (to be executed at a high speed). As a result, the entire system may be simulated. The simplified description of the peripheral logic is described, in some cases, by way of a hardware description language and in some cases by way of a software programming language such as C language.
In design verification using a simulator, the behavior of the circuit under verification and the peripheral logic is executed according to a test pattern to obtain output values. The obtained output value and the contents of an internal register or memory are compared with expected values to thereby determine whether the circuit under verification operates correctly (as designed). The xe2x80x9cexpected valuesxe2x80x9d (predicted outcome) of the circuit under verification may be obtained by previous manual calculation or by using a special program for calculation of the expected value. An expected value calculation program may be connected to a simulator to calculate each expected value when a circuit under verification is executed for simulation. Such an expected value calculation program is described by way of a hardware description language in some cases and by way of a software programming language (such as C or C++) in other cases.
However, in the case of the conventional design method, considerable amounts of time (man-months) are typically required to develop a peripheral logic description and an expected value calculation program of a circuit under verification, which is prepared before the design verification of a piece of hardware. A highly accurate peripheral logic description and expected value calculation program are required because of the high speed and complex logic of the circuit under verification. This complexity requires an extensive amount of time to prepare the verification environment.
A need has been recognized in the art, therefore, to shorten the time requirement of the preparation stage in simulation of the logic circuit system. There also may exist a need to provide a method for generating a behavior model description of a circuit and the software that promptly generates a behavior model description of a circuit including the timing information of various input/output signals.
Further, there has been recognized a need in the art to provide a method for generating a behavior model description of a circuit and the software that promptly generates a highly accurate expected value that is desired for verification of a circuit module. A need has also been identified to provide a logic verification apparatus that can be used to promptly verify the design result of a circuit module. Further, there may exist a need to provide a logic verification apparatus that is capable of prompt verification of the design result of a component circuit module that is combined with one or a plurality of peripheral (e.g., known, old) circuit modules to form one logic system.
To address one or more of the above-mentioned needs, in at least one aspect of the present invention, a behavior model description of a circuit required by a simulator is automatically generated by use of a system level functional description of a circuit module and an interface description of the circuit module as input.
The present invention preferably provides a method for generating a behavior model of a circuit comprising the steps of: reading an interface description that defines state transition of a group of input/output signals of a circuit module at the clock cycle accuracy (wherein xe2x80x9cat the clock cycle accuracyxe2x80x9d herein assumes that all necessary signal and/or data lines have reached a steady state value upon a clock edge); reading a functional description that defines the processing functionality of signals or data of the circuit module as a program function for each processing functionality; and generating a behavior model description of a circuit that defines in-circuit behavior and state transition of input/output signals at clock cycle accuracy by incorporating the content of the program functions defined with the functional description into the state transition of the input/output signals defined with the interface description.
Furthermore, the present invention preferably provides a logic verification apparatus with a means for automatically generating a behavior model description that defines in-circuit behavior of the logic circuit and state transition of input/output signals at clock cycle accuracy, based on an interface description that defines the state transition of a group of input/output signals of the logic circuit and a functional description that defines the processing function of signals or data of a logic circuit regardless of clock operation.
When the means for generating the behavior model description generates a behavior model description of a logic circuit under verification, the behavior model description is a computation model for expected values of the logic circuit under verification. Therefore, it may be possible to verify the behavior of a hardware logic circuit realized according to the logic design data, based on the behavior model description and the logic design data (expected values) of the logic circuit that has been previously prepared.
The means for generating a behavior model description may also generate a behavior model description of a peripheral circuit. Therefore, the first behavior model description is preferably generated from an interface description and a functional description of the logic circuit under verification, and the second behavior model description is generated from an interface description and a functional description of a peripheral circuit connected to the logic circuit. Thereby, it may be possible to verify the circuit behavior realized according to the logic design data, based on the automatically generated first and second behavior models and the logic design data of the logic circuit that has been previously prepared.
Furthermore, the invention preferably provides, in at least one presently preferred embodiment, a computer-readable recording medium including software for generating a behavior model of a circuit which comprises the steps of:
(1) reading an interface description that defines the state transition of a group of input/output signals of a circuit module at clock cycle accuracy from an external file;
(2) converting the correlative relation between the input/output signal combination and the state name for each clock cycle defined in the interface description;
(3) generating a function name including a plurality of internal variables based on the input/output signal definition in the interface description;
(4) generating a deterministic finite state machine formed by modeling the state transition of the circuit module based on the state transition definition of input/output signal in the interface description; and
(5) converting the behavior of the deterministic finite state machine to a program function according to a predetermined rule, by selectively referring to the functional description file that defines the processing function of the signal or data of the circuit module.
Other potential features and advantages of various embodiments of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings and attached claims.